galagino_S3

(version 1)
# Custom Design Rules (DRC) for KiCAD 8.0 (Stored in '<project>.kicad_dru' file).
#
# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities
#
# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules
#
# Inspiration
# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments)
# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments)

# TODO new rule: NPTH pads.
# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter.
# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)."

# TODO: new rule for plated slots: min diameter/width 0.5mm
# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad."

# TODO new rule: non-plated slots: min diameter/width 1.0mm
# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""


# --- Drill/Hole Size ---

(rule "JLCPCB: Drill Hole Size"
  # Choose between:
  # 1-2 Layers
	# (constraint hole_size (min 0.3mm) (max 6.3mm))
  # 4-6 Layers (more costly)
	# (constraint hole_size (min 0.15mm) (max 6.3mm))
  # 4-6 Layers (preferred)
	(constraint hole_size (min 0.2mm) (max 6.3mm))
)

(rule "JLCPCB: Via Hole Size"
	(condition "A.Type == 'Via'")
  # Choose between:
  # 1-2 Layers
	# (constraint hole_size (min 0.3mm))
  # 4-6 Layers (more costly)
  # (constraint hole_size (min 0.15mm))
  # 4-6 Layers (preferred)
	(constraint hole_size (min 0.2mm))
)

(rule "JLCPCB: Via Annular Ring"
	(condition "A.Type == 'Via'")
  # Choose between:
  # 1-6 Layers
  # (constraint annular_width (min 0.05mm))
  # 1-6 Layers (preferred)
	(constraint annular_width (min 0.075mm))
)

(rule "JLCPCB: PTH Hole Size"
	(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated()")
	(constraint hole_size (min 0.2mm) (max 6.3mm))
)

(rule "JLCPCB: NPTH Hole Size"
	(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm.
(rule "JLCPCB: Castellated Hole Size"
	(layer outer)
	(condition "A.Type == 'Pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

(rule "JLCPCB: PTH Annular Ring"
	(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated()")
	(constraint annular_width (min 0.075mm))
)

(rule "JLCPCB: NPTH Annular Ring"
	(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated()")
	(constraint annular_width (min 0.25mm))
)

# An expensive 4-Wire Kelvin Test is automatically added for holes that are < 0.3mm with a diameter ≤ 0.4mm.
(rule "JLCPCB: Avoid 4-Wire Kelvin Test"
	(condition "(A.Type == 'Via' && A.Hole < 0.3mm && A.Diameter <= 0.4mm) || (A.Type == 'Pad' && ((A.Hole_Size_X < 0.3mm && A.Size_X <= 0.4mm) || (A.Hole_Size_Y < 0.3mm && A.Size_Y <= 0.4mm)))")
  # 4-6 Layers
  (constraint annular_width (min 0.125mm))
)


# --- VIA Support Rules --- 

(rule "JLCPCB: Only Throughhole VIAs are supported" 
	(condition "A.Type == 'Via'")
	(constraint assertion "!(A.isBlindBuriedVia() || A.isMicroVia())")
)


# --- Minimum Clearance ---

(rule "JLCPCB: Hole to Hole Clearance (Different Nets)"
	(condition "A.Net != B.Net")
	(constraint hole_to_hole (min 0.5mm))
)

(rule "JLCPCB: Via Hole to Via Hole Clearance (Same Net)"
	(condition "A.Type == 'Via' && B.Type == 'Via' && A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "JLCPCB: Pad to Pad Clearance (Pad without Hole, Different Nets)"
	(condition "A.Type == 'Pad' && (A.Pad_Type != 'Through-hole' && A.Pad_Type != 'NPTH, mechanical') && B.Type == 'Pad' && (B.Pad_Type != 'Through-hole' && B.Pad_Type != 'NPTH, mechanical') && A.Net != B.Net")
	(constraint clearance (min 0.127mm))
)

(rule "JLCPCB: Pad Hole to Pad Hole Clearance (Pad with Hole, Different Nets)"
	(condition "A.Type == 'Pad' && (A.Pad_Type == 'Through-hole' || A.Pad_Type == 'NPTH, mechanical') && B.Type == 'Pad' && (B.Pad_Type == 'Through-hole' || B.Pad_Type == 'NPTH, mechanical') && A.Net != B.Net")
	(constraint hole_to_hole (min 0.5mm))
)

# NOTE: This is not stated specifically, but is implied by other rules.
(rule "JLCPCB: Via/Pad to Via/Pad Clearance (Different Nets)"
	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
	(constraint clearance (min 0.127mm))
)

# NOTE: This is not stated specifically, but is implied by other rules.
(rule "JLCPCB: Via/Pad Hole to Via/Pad Hole Clearance (Same Net)"
	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "JLCPCB: Via to Trace"
	(condition "A.Type == 'Via' && B.Type == 'Track'")
	(constraint hole_clearance (min 0.254mm))
)

(rule "JLCPCB: PTH to Trace"
	(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated() && B.Type == 'Track'")
	(constraint hole_clearance (min 0.33mm))
)

(rule "JLCPCB: NPTH to Trace"
	(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated() && B.Type == 'Track'")
	(constraint hole_clearance (min 0.254mm))
)

(rule "JLCPCB: Pad to Trace"
	(condition "A.Type == 'Pad' && (A.Pad_Type == 'Through-hole' || A.Pad_Type == 'NPTH, mechanical') && B.Type == 'Track' &&  A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)


# --- Minimum Trace Width and Spacing ---

(rule "JLCPCB: Trace Width (Outer Layer)"
	(layer outer)
	(condition "A.Type == 'Track'")
  # Choose between:
  # 1-2 Layers (1oz)
  # (constraint track_width (min 0.127mm))
  # 4-6 Layers (1oz and 0.5oz)
	(constraint track_width (min 0.09mm))
  # 1-6 Layers (2oz)
  # (constraint track_width (min 0.2mm))
)
(rule "JLCPCB: Trace Spacing (Outer Layer)"
	(layer outer)
	(condition "A.Type == 'Track' && B.Type == 'Track'")
  # Choose between:
  # 1-2 Layers (1oz)
  # (constraint clearance (min 0.127mm))
  # 4-6 Layers (1oz and 0.5oz)
	(constraint clearance (min 0.09mm))
  # 1-6 Layers (2oz)
  # (constraint clearance (min 0.2mm))
)

(rule "JLCPCB: Trace Width (Inner Layer)"
	(layer inner)
	(condition "A.Type == 'Track'")
  # Choose between:
  # 4-6 Layers (1oz and 0.5oz)
	(constraint track_width (min 0.09mm))
  # 4-6 Layers (2oz)
  # (constraint track_width (min 0.2mm))
)
(rule "JLCPCB: Trace Spacing (Inner Layer)"
	(layer inner)
	(condition "A.Type == 'Track' && B.Type == 'Track'")
  # Choose between:
  # 4-6 Layers (1oz and 0.5oz)
	(constraint clearance (min 0.09mm))
  # 4-6 Layers (2oz)
  # (constraint clearance (min 0.2mm))
)


# --- Legend ---

(rule "JLCPCB: Minimum Line Width"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
)

(rule "JLCPCB: Minimum Text Height"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_height (min 1mm))
)

(rule "JLCPCB: Pad to Silkscreen"
	(condition "A.Type == 'Pad' && ((A.existsOnLayer('F.Mask') && B.Layer == 'F.Silkscreen') || (A.existsOnLayer('B.Mask') && B.Layer == 'B.Silkscreen')) ")
	(constraint silk_clearance (min 0.15mm))
)


# --- Board Outlines ---

(rule "JLCPCB: Trace to Board Edge"
	(condition "A.Type == 'Track'")
  # Choose between:
  # Routed
	(constraint edge_clearance (min 0.3mm))
  # V-Cut Panel
	# (constraint edge_clearance (min 0.4mm))
)